A Test Chip for Automatic Reliability Measurements of Interconnect Vias
نویسنده
چکیده
For modern VLSI/ULSI fabrication the use of multilevel interconnects is of crucial importance. For electromigration reliability characterizations, time-consuming stress measurements have to be carried out [1,2]. During these measurements a via-hole chain is stressed because of high temperature and high current densities, and the resistance is determined. This type of measurement usually takes much measurement equipment, e.g. current sources, heating equipment and voltmeters. In this paper the design and verification of a test chip that allows automation of via stress measurements and reduces the number of used measurement instruments is described.
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